Nano-Net 2007 Technical Program
The program schedule is subject to change.
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Monday, September 24, 2007
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8:00 am
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Registration
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9:00 am - 10:00 am
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Keynote 1: El-Hang Lee - Micro/Nano-Scale Optical Circuits and Networks: A New Challenge Toward Next Generation
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10:00 am - 10:30 am
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Break
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10:30 am - 12:30 pm
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Session 1: Nanoscale Architecture and Coding
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10:30 am
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Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder
Helia Naeimi , Andre DeHon
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11:00 am
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Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip
Teijo Lehtonen , Pasi Liljeberg , Juha Plosila
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11:30 am
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A 90nm CMOS Cryptographic Core with Improved Fault-Tolerance in Presence of Massive Defect Density
Alexandre Schmid
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12:00 pm
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Integrated Waveguides for Ultra-High Speed Interconnects (invited)
D. Urbano, E. Arnieri, G. Cappuccino, G. Amendola
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12:30 pm - 2:00 pm
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Lunch
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2:00 pm - 3:30 pm
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Session 2: Optical Networks and NEMS
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2:00 pm
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Semi-Analytic Model for Dispersion Relation of Nanowire Lasers
Mohammad Karami
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2:30 pm
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Spectral Sensing with Coupled Nanoscale Oscillators
Nikolai Nefedov
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3:00 pm
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Suspended-gate MOSFET for low standby power switch and memory applications (invited)
D. Tsamados, A.M. Ionescu
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3:30 pm - 4:00 pm
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Break
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4:00 pm - 5:30 pm
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Session 3: Networks-on-Chip - Implementation Issues
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4:00 pm
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A methodology and a case-study for Network-on-Chip based MP-SoC
Sergio Tota , Mario Casu , Maurizio Zamboni , Paolo Motto , Massimo Roch
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4:30 pm
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Relieving physical issues in new NoC-based SoC
Daniele Mangano
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5:00 pm
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Dual-Channel Binary-Countdown Medium Access Control in Wireless Network-on-Chip
Danella Zhao
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6:00 pm - 8:00 pm
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Reception (TBD)
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Tuesday, September 25, 2007
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8:30 am
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Registration
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9:00 am - 10:00 am
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Keynote 2:
TBD (ST)
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10:00 am - 10:30 am
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Break
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10:30 am - 12:30 pm
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Session 4: Networks-on-Chip - Topology Issues
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10:30 am
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A Topology Design Customization Approach for STNoC
Gianluca Palermo , Riccardo Locatelli , Marcello Coppola , Cristina Silvano
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11:00 am
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Algorithm for the Choice of Topology in Reconfigurable On-Chip Networks with Real-Time Support
Kristina Kunert , Mattias Weckstén , Magnus Jonsson
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11:30 am
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Topology-Unaware Routing in Irregular Self-Assembled Networks-on-Chip: An Explorative Case Study
Christof Teuscher
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12:00 pm
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Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow
Igor Loi
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12:30 pm - 2:00 pm
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Lunch
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2:00 pm - 3:30 pm
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Session 5: Optoelectronic Nanodevices
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2:00 pm
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Au, Ag and Cu-Silicon RCE photodetectors based on the internal photoemission effect at 1.55 micron
Maurizio Casalino, L. Sirleto, L. Moretti, Francesco Della Corte, I. Rendina
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2:30 pm
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Raman Approach in Silicon Nanostructure at 1.5 micron
L. Sirleto, Maria Ferrara, B. Jalali, I. Rendina
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3:00 pm
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Design, Fabrication and Characterization of an a-Si:H / SiCN waveguide multistack for electro-optical modulation
Sandro Rao, Maria Nigro, Francesco Suriano, Francesco Della Corte, Caterina Summonte, Alberto Scandurra
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3:30 pm - 4:00 pm
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Break
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4:00 pm - 5:30 pm
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Session 6: Molecular and Atomistic Nanostructures
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4:00 pm
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Development of Molecular based Communication Protocols for Nanomachines
Frank Walsh
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4:30 pm
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Thermodynamic Simulations of DNA Tile Self-Assembly
Kenichi Fujibayashi, Satoshi Murata
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5:00 pm
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Networking Behavior in Thin Film and Nanostructure Growth Dynamics
Murat Yuksel , Tansel Karabacak , Hasan Guclu
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6:00 pm - 8:00 pm
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Social Event (TBD)
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Wednesday, September 26, 2007
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8:30 am
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Registration
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9:00 am - 10:00 am
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Keynote 3:
Eby Friedman - On-Chip Optical Interconnect for Reduced Delay Uncertainty
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10:00 pm - 10:30 pm
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Break
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10:30 am - 12:00 am
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Session 7: Nanoscale Interconnect
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10:30 am
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Asynchronous links (invited)
Alex Yakovlev
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11:00 am
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Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications
Fred Chen , Ajay Joshi , Vladimir Stojanovic , Anantha Chandrakasan
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11:30 am
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Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs
Ravindra Jayanthi , Srinivas Mandalika
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12:00 am - 1:00 pm
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Panel: Nanoscale Networks on Chip
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1:00 pm
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Conference closes
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