Topic: Design Challenges for Nanotechnology-based Nanoelectronics - Can we build systems with nano devices?

Traditional scaling with top-down fabrication:

Scaling of CMOS technology continues in nano scale in spite of tremendous technology development barriers, design challenges and prohibitive costs. Traditional Si CMOS scaling relies on lithography in top-down patterning and manufacturing of transistor building blocks. Technologists are trying to reduce effective oxide thickness, improve channel mobility, and minimize parasitics. Somewhere along the way we may depart from planar CMOS to non-planar device structures such as tri-gate and FinFET thin body transistors to improve device electrostatics to rescue short channel effects.

Design of ICs in these scaled technologies has also faced growing limitations. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. In our traditional scaling path, if we push the top-down manufacturing and lithography to provide us ultra-scaled devices, we will face the problem of increased variations and leakage that will impact circuit and system design

Manufacturing with bottom-up self-assembly:

Another view on fabrication of ultra-scaled devices of the distanced future in molecular dimensions is to use bottom-up self-assembly. If self-assembly and bottom-up manufacturing is a viable option, then we should research nano molecular devices such as nanotubes, nanowires and other novel nano molecular devices? If so, how important are self-assembly and bottom-up manufacturing in making future systems? What does nanotechnology bring to the table? Are we after an alternative fast switch or are we trying to use the self-assembly and bottom-up manufacturing to ease the fabrication cost? Designing with nanotechnology-based switches poses its own challenges. Devices are used in circuits and circuits are used in systems. The question is how do we connect nano devices? How do we build circuits and systems? Do designs utilize the self-assembly and regular fabric nature of these devices & technologies? How do we make contact to nano devices? We would need to research design methodologies for regular fabrics achieved by self-assembled structures and determine how we should go from micro dimensions to nano dimensions to connect to dense nano structures. How should the interconnect system and interfaces be structured? If we rely on bottom-up manufacturing and self-assembly, then we will have to deal with defects and means to do computations and communications in presence of defects.

Benchmarking metrics and hybrid systems:

The way nanotechnology research can directly impact semiconductor industry is to make systems either directly from nano devices and circuits or to impact scaling of silicon CMOS technology using attributes of nanotechnology such as self-assembly and lower manufacturing cost. No matter what, we need ways to evaluate these technologies? What metrics and benchmarks should we be using? Do these technologies meet the following criteria that have provided for success of Si and CMOS technology? That is high gain, good signal to noise, and scaling to reduce cost and energy …

Nanotechnology and nanoelectronics beyond scaled CMOS realistically will not replace silicon and most probably evolve into a hybrid technology along with silicon technology. Will heterogeneous integration of non-Si based nanotechnology onto existing Si technology platform extend CMOS scaling?

Questions posed to panelists to form their positions:

1. We understand that CMOS technology continues to scale. Ignoring traditional CMOS scaling challenges, what are the prospects for alternative nano devices and nano systems? Do you think we need non-planar devices (FinFET and trigate transistor)? How about nanowires and CNTs? Let’s focus on charge-based transport devices and not progress to quantum computing and spintronics, etc.

2. What does nanotechnology bring to the table? Are we after an alternative fast switch or are we trying to use their self-assembly bottom-up manufacturing to ease the fabrication cost? How about memory applications?

3. Devices are used in circuits and circuits are used in systems. The question is how do we connect nano devices? How do we build circuits and systems? Do designs utilize the self-assembly and regular fabric nature of these devices & technologies?

4. Will nanoelectronics replace silicon or evolve into a hybrid technology along silicon? Will heterogeneous integration of non-Si based nanotechnology onto existing Si technology platform extend CMOS scaling?

Panelists:

Organizer: Ali Keshavarzi – Intel

Philip Keukes – HP

Kazuo Yano – Hitachi

Tim Ashley – QinetiQ

Ali Keshavarzi – Intel

Ali Javey – UC Berkeley

Azad Naeemi – Ga Tech

Carlo Pistritto - STMicroelectronics