Keynote speakers

Bio: Philip J. Kuekes joined Hewlett-Packard Laboratories in Palo Alto, California in 1991 as a member of the technical staff. He studied physics at Yale University (1969) and was co-designer of the first commercial array processor at Raytheon Computer (1970-71).

Kuekes was Program Manager and Architect of the Phoenix Systolic Processor, the first high performance, 280 mega-ops, systolic processor (1981). With B.R. Rau and C.D. Glaeser, he patented (1981) a fundamental hardware mechanism to improve scheduling VLIW computers. He was Principal Investigator and Architect of TRW's Systolic Adaptive Beamformer, a 350 Megaflop linear algebra processor (1986). This special purpose processor, funded by DARPA/NTO and the Navy, went to sea in an experiment using adaptive beamforming in towed hydrophone arrays.

Kuekes was Principal Investigator and Architect of the MOSAIC processor, a ten gigaflop heterogeneous supercomputer developed as part of the DARPA/ISTO Strategic Computing Initiative. (1989) He directed a hardware and software development team to create both a gigabyte per second crossbar switch and the dataflow based CAD system to allow a variety of application specific supercomputers to be rapidly configured.

In 1991 Kuekes joined HP Laboratories as Project Manager for Teramac, a trillion operations per second reconfigurable computer. Teramac has been configured to perform DNA sequence matching, volume visualization, and MRI based brain artery detection at 100 times workstation performance. Teramac is the largest defect tolerant processor ever made. Three quarters of the 864 chips in Teramac have defects.

In collaboration with Jim Heath and Stan Williams, Kuekes has recently developed various architectures and interconnect systems for chemically assembled electronic nanocomputers.

Abstract: Nano-technologies will exacerbate the computation and storage densities on chip and require specific strategies for communication. Moreover, the likely array-based structure of computational elements will match well with structured communication means, to increase the predicability of timing behavior. Within this perspective, networks on chip will be the ideal complement to the nano-cores toward achieving high-performance, low-power computational systems.

Bio: Giovanni De Micheli is Professor and Director of the Integrated Systems Centre at EPF Lausanne, Switzerland, and President of the Scientific Committee of CSEM, Neuchatel, Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. He held positions at the IBM T.J. Watson Research Center, Yorktown Heights, New York, at the Department of Electronics of the Politecnico di Milano, Italy and at Harris Semiconductor, Melbourne, Florida. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).

His research interests include several aspects of design technologies for integrated circuits and systems, with particular emphasis on synthesis, system-level design, hardware/software co-design and low-power design. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of six other books and of over 300 technical articles . He is, or has been, member of the technical advisory board of several companies, including Magma Design Automation, Coware, Aplus Design Technologies, Ambit Design Systems and STMicroelectronics.

Dr. De Micheli is the recipient of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He is a Fellow of ACM and IEEE. He received the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000. He received the 1987 D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS, two Best Paper Awards at the Design Automation Conference, in 1983 and in 1993, and a Best Paper Award at the DATE Conference in 2005.

He was President of the IEEE CAS Society in 2003, and he is currently President Elect of the IEEE Council on EDA and chairing the IEEE Product Package Committee . He is Program Chair of the pHealth and VLSI SOC conferences in 2006.

He was Editor in Chief of the IEEE Transactions on CAD/ICAS in 1987-2001. Dr. De Micheli was the Program Chair and General Chair of the Design Automation Conference (DAC) in 1996-1997 and 2000 respectively. He was the Program and General Chair of the International Conference on Computer Design (ICCD) in 1988 and 1989 respectively. He was also co-director of the NATO Advanced Study Institutes on Hardware/Software Co-design, held in Tremezzo, Italy, 1995 and on Logic Synthesis and Silicon Compilation, held in L'Aquila, Italy, 1986. He is a founding member of the ALaRI institute at Universita' della Svizzera Italiana (USI), in Lugano, Switzerland, where he is currently scientific counselor.